Semiconductor intergrated circuit

ABSTRACT

A semiconductor integrated circuit which realizes a reception circuit that can stably detect symbol values even in a case where, in the reception of serial transmission data, the serial transmission data has its phase shifted relative to the sampling clock signals or has its waveform degraded due to the deviation of the delay of a signal in a transmission line. The semiconductor integrated circuit comprises a first clock-signal generating circuit which generates a clock signal of N phases synchronized with an input clock signal, a second clock-signal generating circuit which generates a clock signal of M phases synchronized with one phase selected from among the N-phase clock signal generated by the first clock-signal generating circuit, and in which N≠M holds, and a computation circuit which finds a control value for use in selecting one phase from among the N-phase clock signal, on the basis of the logic value of the serial transmission data sampled using the N-phase clock signal and the M-phase clock signal.

TECHNICAL FIELD

[0001] The present invention relates generally to semiconductorintegrated circuits, and more particularly to a semiconductor integratedcircuit for realizing a reception circuit which receives serialtransmission data.

BACKGROUND ART

[0002] Heretofore, in receiving serial transmission data in thehigh-speed serial transmission of a digital signal (data), a scheme hasbeen generally employed wherein the serial transmission data is sampledby using a sampling clock signal which has a frequency equal to a bitrate of the serial transmission data and which is synchronized with theserial transmission data.

[0003] In accordance with such a simple sampling scheme, however, whensampling the serial transmission data by using the sampling clocksignal, the phase of the serial transmission data is shifted relative tothat of the sampling clock signal due to a deviation of signal delay ina transmission line (this phenomenon is called as “skew”), or thewaveform of the serial transmission data itself is degraded, so thatsymbol values cannot be perfectly detected in some cases.

[0004] In the design of a reception circuit which receives the digitalsignal serially transmitted at high speed, therefore, a circuittechnique has become important which can stably detect the symbol valueseven in the case where such a degraded serial transmission data has beenreceived.

[0005] In recent years, an oversampling scheme, which detects the symbolvalues at a number of sampling points larger than a number of bits ofthe serial transmission data, has been employed as a sampling schemewhich is effective for stably detecting the symbol values even in thecase of receiving the serial transmission data having the waveformdegraded in the transmission line.

[0006] For example, U.S. Pat. No. 5,802,103 discloses an example of afully duplexed transmission system wherein reception data is detected byusing the oversampling scheme in high-speed serial transmission. Asdisclosed in the document, in the case of using a triple oversamplingscheme, a phase shift of at most 30% can be allowed with respect to asymbol period (which corresponds to the inverse number of a number whichis obtained by multiplying a clock frequency by a number of bits in onedata block) even when the phase of serial transmission data is shiftedrelative to the phase of the sampling clock signals.

[0007]FIG. 1 is a block diagram showing an example of a prior-artreception circuit which employs an oversampling scheme. In this example,a number of bits in one data block is 8 bits, and oversampling isperformed at triple a bit rate of the serial transmission data.

[0008] As shown in FIG. 1, the reception circuit includes a PLL or DLLcircuit 210 which generates from an input clock signal multiphase clocksignals which afford a sampling rate at triple a bit rate of the serialtransmission data, a sampling register 220 which oversamples the serialtransmission data by using the multiphase clock signals, and alogic-value determination circuit 230 which determines symbol values of8 bits included in one data block on the basis of the result of theoversampling.

[0009] The serial transmission data of one block (8 bits) inputted tothe sampling register 220 is oversampled at 24 sampling points, whichare triple the number of symbol bits, and the oversampled data isoutputted as parallel data of 24 bits.

[0010] The logic-value determination circuit 230 executes a probabilitycomputation by using the parallel data, thereby to find the transitionpoints of the serial transmission data. Further, the logic-valuedetermination circuit 230 executes re-sampling for selecting appropriateparallel data of 8 bits from among the 24-bit parallel data obtained bythe oversampling, on the basis of the transition points, thereby tofinally determine the symbol values of 8 bits.

[0011]FIG. 2 is a diagram for explaining operations of the receptioncircuit shown in FIG. 1, in terms of logic values. One data block of theserial transmission data inputted to the reception circuit isoversampled by the multiphase clock signals which have a frequency beingtriple the bit rate thereof, with the result that the sampled data isoutputted as the 24-bit parallel data which reflects the logic values ofthe serial transmission data.

[0012] The probability computation is executed by using the paralleldata, whereby the transition points 201-205 are determined. By way ofexample, when the same logic value is consecutive twice in the sampledparallel data, the existence of the transition point is determined. Thesymbol values of 8 bits are determined from among the 24-bit paralleldata, on the basis of the transition points thus determined.

[0013] In accordance with the oversampling scheme, however, a number ofsampling clocks and a number of sampling circuits increase, so that asubstrate area and a consumption current, which are required in asemiconductor integrated circuit, increase. In the design of asemiconductor integrated circuit employing an oversampling scheme attriple, quadruple or higher, therefore, the problem is coped with byadopting advanced minuter semiconductor technology, but there has been aproblem that a manufacturing cost rises.

DISCLOSURE OF THE INVENTION

[0014] In view of the above, accordingly, an object of the presentinvention is to provide a semiconductor integrated circuit whichrealizes a reception circuit that can stably detect symbol values in thereception of serial transmission data even in the case where the serialtransmission data has its phase shifted relative to the sampling clocksignals or has its waveform degraded due to the deviation of delay of asignal in a transmission line and that can suppress increases in thenumber of sampling clock signals and the number of sampling circuits.

[0015] In order to solve the above problem, a semiconductor integratedcircuit according to a first aspect of the present invention comprises afirst clock-signal generating circuit for generating clock signalshaving N phases and synchronized with an input clock signal; a secondclock-signal generating circuit for generating clock signals having Mphases and synchronized with selected one of the clock signals havingN-phases generated by the first clock-signal generating circuit, whereN≠M; and a computation circuit for obtaining a control value for use inselecting one of the clock signals having N-phases, on the basis oflogic values of serial transmission data sampled by using the clocksignals having N-phases and the clock signals having M-phases.

[0016] Further, a semiconductor integrated circuit according to a secondaspect of the present invention comprises a first clock-signalgenerating circuit for generating clock signals having N phases andsynchronized with an input clock signal; a second clock-signalgenerating circuit for generating clock signals having M phases andsynchronized with the input clock signal; and a computation circuit forobtaining a control value for use in changing a phase relationshipbetween the clock signals having N-phases and the clock signals havingM-phases, on the basis of logic values of serial transmission datasampled by using the clock signals having N-phases and the clock signalshaving M-phases.

[0017] The present invention is characterized by using two groups ofmultiphase clock signals which are synchronized with the input clocksignal and which have different numbers of pulses in a time unit, thatis, different frequencies. A first group of multiphase clock signals areused for measuring the phase alignment of the serial transmission data,while a second group of multiphase clock signals are used for measuringthe phase alignment of the serial transmission data and for obtainingthe symbol values of the serial transmission data. The phase of thesecond group of multiphase clock signals is adjusted by using a measuredresult of the phase alignment, whereby the phase of sampling clocksignals can be secured which is always optimal relative to thetransmission data.

[0018] As a result, even in a case where, in the reception of the serialtransmission data, the serial transmission data has its phase shiftedrelative to the sampling clock signals or has its waveform degraded dueto the deviation of the delay of a signal in a transmission line, thesymbol values can be stably detected, and increase in the number ofsampling clock signals or the number of sampling circuits can besuppressed.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The advantages and features of the present invention will becomeapparent when the following detailed description and the drawings areconsidered in association. In these drawings, the same referencenumerals designate the same constituents.

[0020]FIG. 1 is a block diagram showing an example of a prior-artreception circuit which employs an oversampling scheme.

[0021]FIG. 2 is a diagram for explaining operations of the receptioncircuit shown in FIG. 1, in terms of logic values.

[0022]FIG. 3 is a block diagram showing an arrangement of a receptioncircuit which is realized by a semiconductor integrated circuitaccording to a first embodiment of the present invention.

[0023]FIG. 4 is a diagram for explaining operations of the receptioncircuit shown in FIG. 3, in terms of logic values.

[0024]FIG. 5 is a diagram for explaining, in terms of logic valuelevels, an operation in the case where the phase of inputted serialtransmission data shifts relative to that of sampling clock signals inthe reception circuit shown in FIG. 3.

[0025]FIG. 6 is a diagram for explaining an operation after theadjustment of the phase shift shown in FIG. 5, in terms of logic valuelevels.

[0026]FIG. 7A is a diagram showing a number of samples required at aminimum and the phase adjustment range of the serial transmission datain a sampling scheme employed in the present invention, while FIG. 7B isa diagram showing a number of samples required at a minimum and thephase adjustment range of serial transmission data in the oversamplingscheme employed in the prior-art example.

[0027]FIG. 8 is a diagram for explaining, in terms of logic valuelevels, an operation in the case where the phase of the inputted serialtransmission data shifts in an unbalanced fashion relative to that ofthe sampling clock signals in the reception circuit shown in FIG. 3.

[0028]FIG. 9 is a diagram for explaining an operation after theadjustment of the unbalanced phase shift shown in FIG. 8, in terms oflogic value levels.

[0029]FIG. 10 is a block diagram showing an arrangement of a receptioncircuit which is realized by a semiconductor integrated circuitaccording to a second embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0030]FIG. 3 is a block diagram showing arrangement of a receptioncircuit which is realized by a semiconductor integrated circuitaccording to a first embodiment of the present invention. In thisembodiment, a number of bits in one data block is 8 bits, and a phaseadjustment capability is incarnated which is equivalent to or higherthan that in the case of performing oversampling at triple a bit rate ofthe serial transmission data.

[0031] The reception circuit includes a first PLL or DLL circuit 10 forgenerating clock signals having N phases at equal intervals from aninput clock signal, and a second PLL or DLL circuit 20 for generatingclock signals which have M phases at equal intervals and which aresynchronized with one of the N phases of the N-phase clock signals. TheN-phase clock signals are used for measuring phase alignment of theserial transmission data, while the M-phase clock signals are used formeasuring the phase alignment of the serial transmission data and forfinding the symbol values of the serial transmission data. In thisembodiment, 7-phase clock signals are used as the clock signals having Nphases, and 8-phase clock signals as the clock signals having M phases.

[0032] Besides, the reception circuit includes a sampling register 30which samples the serial transmission data at 14 (=N+M−1) samplingpoints that do not coincide between the 7-phase clock signals and the8-phase clock signals. The serial transmission data inputted to thesampling register 30 is paralleled at a bit rate which is 1.75 times ashigh as a number of symbol bits, and the parallel data are outputted assample data of 14 bits.

[0033] Further, the reception circuit includes an alignment computationcircuit 40 which executes a probability computation by using theinputted 14-bit sample data, thereby to finally determine symbol valuesof 8 bits, an alignment shift value and a transmission quality value.The alignment shift value, which is outputted from the alignmentcomputation circuit 40, is fed to the second PLL or DLL circuit 20.

[0034]FIG. 4 is a diagram for explaining operations of the receptioncircuit shown in FIG. 3, in terms of logic values. The inputted serialtransmission data is sampled at a first group of sampling points 11-17which equally divide the period of one data block (8 bits) by 7, and asecond group of sampling points 21-28 which equally divide the period ofone data block by 8, and as a result the sampled data is outputted assample data 31, 32 a, 32 b, 33 a, 33 b, 34 a, 34 b, 35, 36 a, 36 b, 37a, 37 b, 38 a and 38 b of 14 bits.

[0035] The alignment computation circuit 40 shown in FIG. 3 computes theshift value of the serial transmission data from the appropriate phasealignment position thereof by using the 14-bit sample data.

[0036] There will now be described an example of the methods ofcomputing the shift value of the serial transmission data from theappropriate phase alignment position thereof.

[0037] First, values in the internal registers 41-47 of the alignmentcomputation circuit are reset to “0”. Subsequently, the alignmentcomputation circuit decides whether or not the logic value of the sampledata 32 a is equal to that of the sample data 32 b, and it stores “−1”in the internal register 42 if the logic values are equal to each other.Likewise, the alignment computation circuit decides whether or not thelogic value of the sample data 33 a is equal to that of the sample data33 b, and it stores “−1” in the internal register 43 if the logic valuesare equal to each other. Likewise, the alignment computation circuitdecides whether or not the logic value of the sample data 34 a is equalto that of the sample data 34 b, and it stores “−1” in the internalregister 44 if the logic values are equal to each other.

[0038] On the other hand, the alignment computation circuit decideswhether or not the logic value of the sample data 36 a is equal to thatof the sample data 36 b, and it stores “+1” in the internal register 45if the logic values are equal to each other. Likewise, the alignmentcomputation circuit decides whether or not the logic value of the sampledata 37 a is equal to that of the sample data 37 b, and it stores “+1”in the internal register 46 if the logic values are equal to each other.Likewise, the alignment computation circuit decides whether or not thelogic value of the sample data 38 a is equal to that of the sample data38 b, and it stores “+1” in the internal register 47 if the logic valuesare equal to each other.

[0039] The alignment shift value, which represents the shift magnitudeof the serial transmission data from the appropriate phase alignmentposition thereof, can be computed by finding the summation of the valuesrespectively stored in the internal registers 41-47. In the case wherethe serial transmission data exists at the appropriate phase alignmentposition, the alignment shift value becomes “0”. Besides, the qualityvalue, which represents the quality of a transmission line, can becomputed by finding the summation of the absolute values of the valuesrespectively stored in the internal registers 41-47. In the case wherethe quality of the transmission line is good, the transmission qualityvalue becomes “6”.

[0040] Simultaneously, the symbol values which are obtained by samplingthe serial transmission data at the second group of sampling points21-28 that equally divide the period of one data block by 8 is outputtedas detection signals.

[0041] Next, there will be described another example of the methods ofcomputing the shift value of the serial transmission data from theappropriate phase alignment position thereof.

[0042] Although “0”, “−1” or “+1” is stored in each of the internalregisters 41-47 in the foregoing example, “0” or “1” is stored in eachof the internal registers 41-47 in this example. More specifically, thealignment computation circuit stores “1” in each internal register ifthe logic values of two sample data to be compared are equal to eachother. Thereafter, the alignment computation circuit finds a sum SUM1 ofvalues respectively stored in the internal registers 41-44 and a sumSUM2 of values respectively stored in the internal registers 45-47 so asto find a difference (SUM2−SUM1) of the sums. Thus, the alignmentcomputation circuit can compute the alignment shift value whichrepresents the shift magnitude of the serial transmission data from theappropriate phase alignment position thereof.

[0043]FIG. 5 is a diagram for explaining, in terms of logic valuelevels, operations in the case where the phase of the inputted serialtransmission data shifts relative to that of the sampling clock signalsin the reception circuit according to this embodiment. Such a situationis an example of degradation which occurs for the reason that a signaldelay time in the transmission line differs between the serialtransmission data and the clock signal.

[0044] The inputted serial transmission data is sampled at the firstgroup of sampling points 11-17 and the second group of sampling points21-28 which groups share one sampling point, and as a result the sampleddata is outputted as sample data 51, 52 a, 52 b, 53 a, 53 b, 54 a, 54 b,55, 56 a, 56 b, 57 a, 57 b, 58 a and 58 b of 14 bits.

[0045] Since the phase alignment of the serial transmission data to thesampling clock signals shifts, the summation of values respectivelystored in the internal registers 41-47 in the alignment computationcircuit, namely, the alignment shift value is obtained to be “+2” ratherthan “0”. The phase alignment is adjusted in such a way that a clocksignal to be selected as a reference phase from among the inputted7-phase clock signals is altered on the basis of the alignment shiftvalue in the second PLL or DLL circuit 20 (FIG. 3) which generates thesampling clock signals. Besides, the summation of the absolute values ofthe values respectively stored in the internal registers 41-47 in thealignment computation circuit, namely, the transmission quality value isobtained to be “4” rather than “6”. This indicates that the quality ofthe reception data is lowered under the influences of the transmissionline, etc.

[0046]FIG. 6 is a diagram for explaining operations after the adjustmentof the phase shift shown in FIG. 5, in terms of logic value levels.Since the computed alignment shift value is “+2” in FIG. 5, the clocksignal to be selected in the second PLL or DLL circuit 20 (FIG. 3) isshifted by “−2”, whereby the clock signal affording the sampling point11 is altered to the clock signal affording the sampling point 16, andthe internal registers 41-47 are reset. Alternatively, the clock signalto be selected may well be determined after computed alignment shiftvalues are integrated over a predetermined time period and thenaveraged.

[0047] The inputted serial transmission data is sampled at the samplingpoints arrayed anew, and as a result the sampled data is outputted assample data 63 a, 63 b, 64 a, 64 b, 65, 66 a, 66 b, 67 a, 67 b, 68 a, 68b, 61, 62 a and 62 b of 14 bits. Thereafter, the alignment shift valueis computed again by using values respectively stored in the internalregisters 41-47. Since the reference sampling point has shifted by “−2”,the alignment shift value becomes “0” again. Besides, the transmissionquality value is resumed to “6”.

[0048] As described above, the phase relationship between the serialtransmission data and the sampling clock signals is always adjusted byusing the computed result in the alignment computation circuit, wherebythe symbol values can be stably detected against the degradation (suchas the skew) of the signal waveform in the transmission line on thebasis of a small number of data samplings.

[0049]FIG. 7A shows the number of samples required at a minimum and thephase adjustment range of the serial transmission data in the samplingscheme using the N-phase clock signals and the M-phase clock signals asis employed in the present invention. On the other hand, FIG. 7B showsthe number of samples required at a minimum and the phase adjustmentrange of the serial transmission data in the X-fold oversampling schemeemployed in the prior-art example. It is understood by comparing boththe sampling schemes that, when (M/N−1) is smaller than ⅓ in the case ofN<M, the scheme employed in the present invention is capable of finerphase adjustments than the triple oversampling scheme employed in theprior-art example. Incidentally, N>M may well be set, and in that case,when (N/M−1) is smaller than ⅓, the scheme employed in the presentinvention becomes capable of finer phase adjustments than the tripleoversampling scheme employed in the prior-art example.

[0050]FIG. 8 is a diagram for explaining, in terms of logic valuelevels, operations in the case where the phase of the inputted serialtransmission data shifts in an unbalanced fashion relative to that ofthe sampling clock signals in the reception circuit shown in FIG. 3.Such a situation is an example of degradation which occurs for thereasons that a signal delay time differs between the serial transmissiondata and the clock signal in a balanced transmission line, and that asignal delay time becomes different also between two transmission linesincluded in the balanced transmission line.

[0051] The inputted serial transmission data is sampled at the firstgroup of sampling points 11-17 which equally divide the period of onedata block by 7, and the second group of sampling points 21-28 whichequally divide the period of one data block by 8 in synchronism with oneof the first group of sampling points (the sampling point 11 in FIG. 8),and as a result the sampled data is outputted as sample data 71, 72 a,72 b, 73 a, 73 b, 74 a, 74 b, 75, 76 a, 76 b, 77 a, 77 b, 78 a and 78 bof 14 bits.

[0052] In FIG. 8, since the trailing edges of the inputted serialtransmission data shift relative to the phase of the sampling clocksignals, the alignment shift value computed on the basis of the inputted14-bit sample data in the alignment computation circuit 40 (FIG. 3)results in “+1” rather than “0”. The selection of a clock signal in thesecond PLL or DLL circuit 20, which generates the sampling clocksignals, is altered on the basis of the alignment shift value, wherebythe phase alignment is adjusted.

[0053]FIG. 9 is a diagram for explaining operations after the adjustmentof the unbalanced phase shift shown in FIG. 8, in terms of logic valuelevels. Since the computed alignment shift value is “+1”, the clocksignal to be selected from among the 7-phase clock signals affording thesampling points 11-17 is shifted by “−1”, whereby the clock signal to beselected is altered from the clock signal affording the sampling point11 to the clock signal affording the sampling point 17. Alternatively,the clock signal to be selected may well be determined after computedalignment shift values are integrated over a predetermined time periodand then averaged.

[0054] The inputted serial transmission data is sampled at the samplingpoints arrayed anew, and as a result the sampled data is outputted assample data 82 a, 82 b, 83 a, 83 b, 84 a, 84 b, 85, 86 a, 86 b, 87 a, 87b, 88 a, 88 b and 81 of 14 bits. When the alignment shift value iscomputed by using the sample data, it becomes “0” again because thephase of the sampling clock signals have shifted by “−1”.

[0055] It is to be noted that the alignment shift value has become “0”in FIG. 9, but that the transmission quality value, which is thesummation of the absolute values of the values held in the internalregisters 41-47, is “4” unlike “6” in FIGS. 4 and 6. Unlike in the caseshown in FIG. 5 where the serial transmission data is merely delayedrelative to the sampling clock signals in the balanced transmissionline, in the case where the serial transmission data having the inferiorwaveform is received because the delay time becomes different alsobetween the two transmission lines included in the balanced transmissionline, the transmission quality value becomes smaller even in the statewhere the phase alignment is held.

[0056] In this manner, according to this embodiment, the correctingdirection of the phase alignment can be known by finding the summationof the values stored in the internal registers of the alignmentcomputation circuit, and moreover, the quality of the transmission linecan be grasped by finding the summation of the absolute values of thevalues stored in the internal registers of the alignment computationcircuit.

[0057] In the general serial transmission line, it can easily occur thatthe quality of the transmission line fluctuates dynamically. In thiscase, if the quality (the degree of degradation) of the transmissionline can be measured by a simple method, it is permitted to select atransmission method which corresponds to the quality of the transmissionline. In, for example, a transmission line severely degraded, atransmission circuit is controlled to transmit serial transmission databy lowering a bit rate, whereby the stable transmission of the serialtransmission data becomes possible. Likewise, it is possible to select areception method which corresponds to the quality of the transmissionline. For example, in a transmission line severely degraded, the gain ofthe initial stage of an amplifier is increased or waveform equalizationis performed in a reception circuit, whereby the stable reception ofserial transmission data becomes possible.

[0058] In accordance with this embodiment, it is permitted to realizethe reception circuit which has the phase adjustment capabilityequivalent to or higher than that of the prior-art oversampling scheme,by using the clock signals which are much smaller in number than theclock signals required for the oversampling scheme. Thus, a performancewhich is equivalent to or higher than that of the oversampling schemecan be incarnated with lower consumption power.

[0059] Further, although the dynamic measurement of the quality of theserial transmission data has been difficult in the prior-artoversampling scheme, it is easily permitted in accordance with thisembodiment. Thus, this embodiment can be dynamically adapted to thequality of the transmission line.

[0060] In this embodiment, there has been described the example whichemploys the PLL or DLL circuit in order to generate the N-phase clocksignals synchronized with the input clock signal, and which employs thePLL or DLL circuit in order to generate the M-phase clock signalssynchronized with one selected clock signal from among the N-phase clocksignals. However, the present invention is realizable and effective evenwhen another circuit, which can generate the multiphase clock signalshaving equal phase intervals, is employed. Besides, as to the number ofthe multiphase clock signals, the present invention is realizable andeffective no matter what values are employed for N and M as long as N≠M.

[0061] Next, a semiconductor integrated circuit according to a secondembodiment of the present invention will be described. This embodimentis such that the present invention is applied to a reception circuithaving 3 channels for RGB digital image signals. In this embodiment, thenumber of bits of one data block is 10, and a phase adjustmentcapability is bestowed which is equivalent to or higher than that ofquadruple oversampling.

[0062]FIG. 10 is a block diagram showing the arrangement of thereception circuit which is realized by the semiconductor integratedcircuit according to the second embodiment of the present invention.

[0063] The reception circuit includes a common circuit block 100C, anR-channel circuit block 100R, a G-channel circuit block 100G and aB-channel circuit block 100B.

[0064] An inputted balanced clock signal and balanced serialtransmission data of 3 channels are respectively amplified bydifferential amplifiers 90-93. Each of the differential amplifiers 90-93has the function of adjusting the gain of its initial stage inaccordance with a control signal supplied from a control circuit 50. Ina first DLL circuit 110, the amplified balanced clock signal isconverted into alignment measuring clock signals having 9 phases atequal intervals and synchronized with the inputted balanced clocksignal.

[0065] In a clock-signal selection circuit 70 which is controlled by aphase alignment circuit 60, one clock signal is selected from among the9-phase clock signals outputted from the first DLL circuit 110. A secondDLL circuit 120 outputs symbol sampling clock signals having 10 phasesand synchronized with the inputted balanced clock signal, on the basisof the selected clock signal.

[0066] The 9-phase clock signals subjected to wave-shaping in a localbuffer 80 and the 10-phase clock signals outputted from the second DLLcircuit 120 are inputted to a sampling circuit 130. The sampling circuit130 samples the serial transmission data amplified by the differentialamplifier 91 on the basis of the inputted clock signals, so as to outputsample data of 18 (=10+9−1) bits.

[0067] The phase alignment circuit 60 obtains an alignment shift value,which represents information on the phase alignment of the serialtransmission data, on the basis of the sampling data of 18 bits, and itfeeds this alignment shift value back to the clock-signal selectioncircuit 70.

[0068] Simultaneously, the phase alignment circuit 60 finds atransmission quality value, which represents information on thetransmission quality of the serial transmission data, on the basis ofthe sampling data of 18 bits, and it feeds this transmission qualityvalue back to the control circuit 50. The control circuit 50 sets thegains of the initial stages of the differential amplifiers 90-93 on thebasis of the transmission quality values for the 3 channels, wherebygain adjustments can be made in correspondence with the transmissionqualities of the serial transmission data.

[0069] On the other hand, data of 10 bits sampled by using the samplingclock signals outputted from the second DLL circuit 120 are subjected tobit position alignment by a word alignment circuit 90, and they arethereafter outputted as parallel data.

[0070] Although the R-channel circuit blocks in the circuit blocks ofthe 3 channels of R, G and B have been described above, each of theremaining 2 channels is constructed of similar circuit blocks. Thus,even when the serial transmission data of the 3 channels haveindependently undergone phase delays relative to the clock signal, thetransmission data can be stably received by employing the receptionapparatus according to this embodiment.

[0071] Although the present invention has thus far been described inconjunction with the embodiments, it can be freely modified and alteredwithin a scope defined in the claims, without being restricted to theseembodiments.

INDUSTRIAL APPLICABILITY

[0072] A semiconductor integrated circuit according to the presentinvention is applicable in a device, such as liquid crystal display,having a reception circuit which receives serial transmission data.

1. A semiconductor integrated circuit comprising: a first clock-signalgenerating circuit for generating clock signals having N phases andsynchronized with an input clock signal; a second clock-signalgenerating circuit for generating clock signals having M phases andsynchronized with selected one of the clock signals having N phasesgenerated by said first clock-signal generating circuit, where N≠M; anda computation circuit for obtaining a control value for use in selectingone of the clock signals having N phases, on the basis of logic valuesof serial transmission data sampled by using the clock signals having Nphases and the clock signals having M phases.
 2. A semiconductorintegrated circuit according to claim 1, wherein said secondclock-signal generating circuit selects one of the clock signals havingN phases generated by said first clock-signal generating circuit, as aclock signal defining a reference phase, on the basis of the controlvalue obtained by said computation circuit.
 3. A semiconductorintegrated circuit according to claim 1, wherein said first clock-signalgenerating circuit generates the clock signals having N phases at equalintervals, and said second clock-signal generating circuit generates theclock signals having M phases at equal intervals.
 4. A semiconductorintegrated circuit according to claim 1, wherein at least one of saidfirst clock-signal generating circuit and said second clock-signalgenerating circuit includes either one of a phase locked loop circuitand a delay locked loop circuit.
 5. A semiconductor integrated circuitaccording to claim 1, wherein said first clock-signal generating circuitincludes a phase locked loop circuit, and said second clock-signalgenerating circuit includes a delay locked loop circuit.
 6. Asemiconductor integrated circuit according to claim 1, wherein saidfirst clock-signal generating circuit includes a delay locked loopcircuit, and said second clock-signal generating circuit includes aphase locked loop circuit.
 7. A semiconductor integrated circuitcomprising: a first clock-signal generating circuit for generating clocksignals having N phases and synchronized with an input clock signal; asecond clock-signal generating circuit for generating clock signalshaving M phases and synchronized with the input clock signal; and acomputation circuit for obtaining a control value for use in changing aphase relationship between the clock signals having N phases and theclock signals having M phases, on the basis of logic values of serialtransmission data sampled by using the clock signals having N phases andthe clock signals having M phases.
 8. A semiconductor integrated circuitaccording to claim 7, wherein said second clock-signal generatingcircuit shifts a phase of the clock signals having M phases by using asan unit of time period a phase difference period of the clock signalshaving N phases as an unit of time period, on the basis of the controlvalue obtained by said computation circuit.
 9. A semiconductorintegrated circuit according to claim 7, wherein the clock signalshaving N phases and the clock signals having M phases respectivelygenerated by the first and second clock-signal generating circuitsdefine (N+M−1) different sampling points which include one commonsampling point in one cycle of the input clock signal.
 10. Asemiconductor integrated circuit according to claim 9, wherein saidcomputation circuit obtains a summation of values respectivelycorresponding to a plurality of combinations of predetermined 2 bits in(N+M−1) bits of parallel data which have been obtained by sampling theserial transmission data at the (N+M−1) different sampling points,thereby to obtain the control value which represents a shift of phasealignment of the serial transmission data relative to the clock signalshaving M phases.
 11. A semiconductor integrated circuit according toclaim 10, wherein said computation circuit uses as the predetermined 2bits of the parallel data, 2 bits which have been sampled at a firstsampling point in N sampling points represented by the clock signalshaving N phases and a second sampling point adjacent to the firstsampling point in M sampling points represented by the clock signalshaving M phases.
 12. A semiconductor integrated circuit according toclaim 9, wherein said computation circuit obtains a summation ofabsolute values of values respectively corresponding to a plurality ofcombinations of predetermined 2 bits in (N+M−1) bits of parallel datawhich have been obtained by sampling the serial transmission data at the(N+M−1) different sampling points, thereby to obtain a value concerninga quality of the serial transmission data.
 13. A semiconductorintegrated circuit according to claim 12, further comprising: anamplifier having a variable gain; and a control circuit for changing thegain of said amplifier on the basis of the value concerning a quality ofthe serial transmission data obtained by said computation circuit.
 14. Asemiconductor integrated circuit according to claim 7, wherein saidfirst clock-signal generating circuit generates the clock signals havingN phases at equal intervals, and said second clock-signal generatingcircuit generates the clock signals having M phases at equal intervals.15. A semiconductor integrated circuit according to claim 7, wherein atleast one of said first clock-signal generating circuit and said secondclock-signal generating circuit includes either one of a phase lockedloop circuit and a delay locked loop circuit.
 16. A semiconductorintegrated circuit according to claim 7, wherein said first clock-signalgenerating circuit includes a phase locked loop circuit, and said secondclock-signal generating circuit includes a delay locked loop circuit.17. A semiconductor integrated circuit according to claim 7, whereinsaid first clock-signal generating circuit includes a delay locked loopcircuit, and said second clock-signal generating circuit includes aphase locked loop circuit.